Semi-insulating polycrystalline silicon (SIPOS) is receiving steadily wider acceptance as the alternative to silicon oxide for the passivation of high voltage silicon devices. A major disadvantage of oxide, long the standard passivation used on silicon, is its highly insulating nature which allows the accumulation of net charge. This leads to the eventual drift of device characteristics. SIPOS on the other hand, has a slight conductivity (10.sup.-7 to 10.sup.-10 ohm-cm) controlled by the degree of oxygen incorporation and hence prevents the appearance of detrimental trapped charges without the introduction of excess leakage current.
U.S. Pat. No. 4,014,037 discloses the use of oxygen doped SIPOS for passivation in semiconductor devices and suitable methods for its deposition. However, it has not previously been noted that the advantages of SIPOS cannot be fully achieved if the interface between the SIPOS and the underlying semiconductor substrate is not under control. In practice, SIPOS is typically deposited by a low pressure chemical vapor deposition (LPCVD) process using SiH.sub.4 and N.sub.2 O with or without N.sub.2 carrier at a temperature of about 625.degree. C. Annealing at about 900.degree. C. for one-half hour results in the appearance of polycrystalline silicon 50 to 100 Angstroms in thickness. Since the permeability of SIPOS to contaminants is quite high, a protective cap of glass, silicon oxide, silicon nitride or other suitable layer is generally used in conjunction with SIPOS.
Using the above noted usual chemical vapor deposition technique for depositing the SIPOS layer, there will inherently be present a layer of "native" oxide approximately 20 Angstroms thick at the interface between the SIPOS and the underlying substrate. This layer is inherently present because of the rapid formation of the oxide when the silicon substrate is exposed to the atmosphere and because no positive steps are taken in the ordinary SIPOS deposition process to remove or insure the absence of such a layer. Such an oxygen-rich interface has indeed been identified by high resolution Auger depth profiling of SIPOS passivated devices constructed in accordance with the standard procedures. The presence of such an oxygen rich layer at the interface between the silicon substrate and SIPOS leads to unexpected interface charges which in turn deteriorate the positive effects of the SIPOS passivation layer and render the operating characteristics of the resultant device at least less predictable, if not erratic.